A Rainy Day - Tunis

Happy new year 2008

ESS vs Boca (part 1 )

ESS vs Boca (part 2 )

ESS vs Boca (part 3 )

Watch Dog Timers

A watchdog timer is a piece of hardware that can be used to automatically detect software anomalies and reset the processor if any occur. Generally speaking, a watchdog timer is based on a counter that counts down from some initial value to zero.

The embedded software selects the counter's initial value and periodically restarts it. If the counter ever reaches zero before the software restarts it, the software is presumed to be malfunctioning and the processor's reset signal is asserted. The processor (and the software it's running) will be restarted as if a human operator had cycled the power.

http://89c51.blogspot.com/

Build Your Own ARM Cross Compiler Toolchain

GNUARM is a set of open source GNU compiler for ARM microcontroller. The toolchain consists of the GNU binutils, GCC compiler set, Newlib and Insight, the graphical user interface to GNU debugger for Windows and Linux. This article will guide the building process of GNUARM toolchain only for Linux users. For Windows users, there have the installer executable EXE files already. www.scienceprog.com has a tutorial on setting up this tool on Windows environment.

Is it possible to hack into a gmail address ? - Really scary

Who doesn't have a gmail id now a days ? In my honest opinion, I am yet to discover a more user friendly web mail host. Gmail is non-intrusive, provides all the advanced and usable features such as POP3, mail search and much more.

But recently at a Black Hat security convention, Robert Graham, the CEO of errata security, surprised attendees by hijacking a Gmail session on camera and reading the victim’s email. He went even further by demonstrating the attack by taking over another journalist’s Gmail account and then sending emails from that account. Really scary.

So how do you protect yourself from somebody sniffing your email while it is in transit and then hacking into your gmail account ? There is one way to make it much harder for sniffing your mails. That is by sending and receiving mails using Gmail's SSL feature. SSL stands for Secure Sockets Layer and is used to provide secure data transfer across the web, for instance ecommerce sites use SSL to transmit your credit card details. Google provides the SSL feature for gmail and all it takes to enable SSL in Gmail is by typing the address https://mail.google.com instead of http://mail.google.com. Make note of the 's' in 'https'. What this does is instead of encrypting only the username and password, Gmail encrypts the whole mail session and this makes it possible to transfer your mails in a secure manner.

So the next time you decide to log on to your gmail account, use https instead of http and you will be fairly safe from getting your mail sniffed in transit.

http://linuxhelp.blogspot.com/

Linux Kernel Development

Developing Video IP in a Fully Integrated Design Environment

Often the implementation of video processing systems requires support for various video and audio standards and involves converting signals from one standard to another. Multimedia applications require processing signals at video rates, whichmeans that simulation should run in realtime during the development process. Typical video processing systems use a microprocessor to control a video pipeline comprising a video source and sink, a large memory for storage of video data, and a video processing system (Figure 1). As you implement and debug the various video algorithms, you will need to verify the functionality through software and hardware simulation. Simulation of video processing applications creates special challenges given the real-time nature of video streams and the enormous amount of video data required per frame.

Figure 1 – Video system diagram

Speech Recognition using FPGA

FPGA Altera

High-Performance Image Processing on FPGAs

The rapid evolution of digital imaging technology, accompanied by huge market demand for cameras and displays in both consumer and industrial segments, presents a significant challenge to device developers who want to create high-quality products. To extract the best possibleimages from capture and display hardware, sophisticated image processing algorithms are available. But their implementation is limited by several factors: the intrinsic complexity of the algorithms; the pressure to reduce bill of materials costs; the need to support a wide variety of developing formats; and the frequent requirement to customize particular device environments. The development and licensing ofimage-processing IP is central to Apical’s business. If the design of a new IP core is hindered by difficulties in coding and verifying RTL, or if a customer has no straightforward way to evaluate and implement the IP in their products, then the initial enthusiasm of an exciting research result rapidly evaporates.

Path Finder, A Real Time Linux Robot

A burning CPU

Successful DDR2 Design

The introduction of the first SDRAM interface, in 1997, marked the dawn of the high-speed memory interface age. Since then, designs have migrated through SDR (single data rate), DDR (double data rate), and now DDR2 memory interfaces to sustain increasing bandwidth needs in products such as graphics accelerators and high-speed routers.
As a result of its highbandwidth capabilities, DDR and DDR2 technology is used in nearly every sector of the electronics design industry from computers and networking to consumer electronics and military applications. DDR technology introduced the concept of “clocking” data in on both a rising and falling edge of a strobe signal in a memory interface. This provided a 2x bandwidth improvement over an SDR interface with the same clock speed. This, in addition to faster clock frequencies, allowed a single-channel DDR400 interface with a 200 MHz clock to support up to 3.2 GB/s, a 3x improvement over the fastest SDR interface. DDR2 also provided an additional 2x improvement in bandwidth over its DDR predecessor by doubling the maximum clock frequency to 400 MHz. Table 1 shows how the progression from SDR to DDR and DDR2 has allowed today’s systems to maintain their upward growth path.



Table 1 – The progression from SDR to DDR and DDR2 has allowed today’s systems to maintain theirupward growth path. Speed grades and bit rates are shown for each memory interface.

C and C++ languages and hardware description

C and C++ have been a popular starting point for developing hardware and systems for many years; the languages are widely known, quick to write, and give an executable specification, which allows for very fast simulation. C or C++ versions of standard algorithms are widely available, so you can easily reuse legacy and publicly available code. For system level design, C and C++ allow you to describe hardware and software descriptions in a single framework.

Two drawbacks exist, however. First, C and C++ do not support the description of some important hardware concepts, such as timing and concurrency. This has led to the development of proprietary C-like languages, which aren’t popular because they tie users to a single software supplier. Second, you must manually translate C and C++ to a hardware description language such as VHDL or Verilog for hardware implementation. This time-consuming step requires hardware experts and often introduces errors that are difficult to find.

The first problem has been solved by the development of SystemC, which now a widely accepted industry standard that adds hardware concepts to C++. The second problem has been solved by the development of tools like SystemCrafter SC, which allows SystemC descriptions to be automatically translated to VHDL.

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